cystech electronics corp. spec. no. : c233k3 issued date : 2013.05.09 revised date : 2013.12.25 page no. : 1/7 BTA1013K3 cystek product specification pnp epitaxial planar transistor BTA1013K3 features ? low v ce(sat) , v ce(sat) = -387mv (typ.) @ i c /i b =-1a/-100ma ? high breakdown voltage, bv ceo =-160v ? complementary to btc2383k3 ? pb-free lead plating and halogen-free package symbol outline BTA1013K3 to-92l b base c collector e emitter ordering information device package shipping to-92l 2000 pcs / tape & box BTA1013K3-0-tb-g (pb-free lead plating and halogen-free package) to-92l BTA1013K3-0-bm-g (pb-free lead plating and halogen-free package) 500 pcs / bag, 10 bags/box, 10 boxes/carton environment friendly grade : s for rohs compliant products, g for rohs compliant and green compound products packing spec, tb : 2000 pcs / tape & box ; bm : 500 pcs/bag, 10 bags/box, 10 boxes/carton product rank, zero for no rank products product name
cystech electronics corp. spec. no. : c233k3 issued date : 2013.05.09 revised date : 2013.12.25 page no. : 2/7 BTA1013K3 cystek product specification absolute maximum ratings (ta=25 c) parameter symbol limits unit collector-base voltage v cbo -160 v collector-emitter voltage v ceo -160 v emitter-base voltage v ebo -7 v collector current (dc) i c -1 a collector current (pulse) i cp -2 (note) a power dissipation p d 0.9 w thermal resistance, junction to ambient r ja 139 c/w operating junction temperature range tj -55~+150 c storage temperature range tstg -55~+150 c note : pulse test, p w 10ms, duty 50%. characteristics (ta=25 c) symbol min. typ. max. unit test conditions bv cbo -160 - - v i c =-100 a bv ceo -160 - - v i c =-10ma bv ebo -7 - - v i e =-10 a i cbo - - -100 na v cb =-160v i ebo - - -100 na v eb =-7v *v ce(sat) 1 - -60 -100 mv i c =-100ma, i b =-10ma *v ce(sat) 2 - -140 -300 mv i c =-500ma, i b =-50ma *v ce(sat) 3 - -387 -750 mv i c =-1a, i b =-100ma *v be(sat) - -0.83 -1.2 v i c =-500ma, i b =-50ma *v be(on) -0.45 - -0.75 v v ce =-5v, i c =-5ma *h fe 1 90 - - - v ce =-5v, i c =-10ma *h fe 2 100 - 200 - v ce =-5v, i c =-200ma f t 50 - - mhz v ce =-10v, i c =-50ma, f=100mhz cob - 13 20 pf v cb =-10v, f=1mhz *pulse test: pulse width 380 s, duty cycle 2%
cystech electronics corp. spec. no. : c233k3 issued date : 2013.05.09 revised date : 2013.12.25 page no. : 3/7 BTA1013K3 cystek product specification typical characteristics emitter grounded output characteristics 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0123456 -vce, collector-to-emitter voltage(v) -ic, collector current(a) 200ua 300ua 400ua 500ua 1ma -ib=100ua emitter grounded output characteristics 0 0.1 0.2 0.3 0.4 0.5 0.6 0123456 -vce, collector-to-emitter voltage(v) -ic, collector current(a) 1.5ma 2ma 2.5ma 5ma -ib=500ua emitter grounded output characteristics 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0123456 -vce, collector-to-emitter voltage(v) -ic, collector current(a) 4ma 6ma 8ma 20ma -ib=2ma emitter grounded output characteristics 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0123456 -vce, collector-to-emitter voltage(v) -ic, collector current(a) 10ma 25ma 50ma -ib=5ma current gain vs collector current 10 100 1000 1 10 100 1000 -ic, collector current(ma) current gain---hfe ta=125c ta= 75c ta= 25c ta=0c ta=-40c vce=-1v current gain vs collector current 10 100 1000 1 10 100 1000 -ic, collector current(ma) current gain---hfe ta=125c ta=75c ta=25c ta=0c ta=-40c vce=-2v
cystech electronics corp. spec. no. : c233k3 issued date : 2013.05.09 revised date : 2013.12.25 page no. : 4/7 BTA1013K3 cystek product specification typical characteristics(cont.) current gain vs collector current 10 100 1000 1 10 100 1000 -ic, collector current(ma) current gain---hfe ta=125c ta=75c ta=25c ta=0c ta=-40c vce=-5v saturation voltage vs collector current 10 100 1000 1 10 100 1000 -ic, collector current(ma) saturation voltage---(mv) ta=125c ta=75c ta=25c ta=0c ta=-40c vcesat@ic=10ib saturation voltage vs collector current 100 1000 10000 1 10 100 1000 -ic, collector currentma) saturation voltage---(mv) vbesat@ic=10ib ta=-40c ta=0c ta=25c ta=75c ta=125c on voltage vs collector current 100 1000 10000 1 10 100 1000 -ic, collector current(ma) on voltage---(mv) vbeon@vce=-1v ta=-40c ta=0c ta=25c ta=75c ta=125c capacitance vs reverse-biased voltage 1 10 100 1000 0.1 1 10 100 -vr, reverse-biased voltage(v) capacitance---(pf) cib cob power derating curve 0 0.3 0.6 0.9 1.2 0 25 50 75 100 125 150 175 ambient temperature---ta() power dissipation---pd(w)
cystech electronics corp. spec. no. : c233k3 issued date : 2013.05.09 revised date : 2013.12.25 page no. : 5/7 BTA1013K3 cystek product specification to-92l taping outline millimeters dim item min. max. a1 component body width 4.70 5.10 a component body height 7.80 8.20 t component body thickness 3.70 4.10 d lead wire diameter 0.35 0.55 d1 lead wire diameter 1 0.60 0.80 p pitch of component 12.40 13.00 p0 feed hole pitch 12.50 12.90 p2 hole center to component center 6.05 6.65 f1, f2 lead to lead distance 2.20 2.80 h component alignment, f-r -1.00 1.00 w tape width 17.50 19.00 w0 hole down tape width 5.50 6.50 w1 hole position 8.50 9.50 w2 hole down tape position - 1.00 h height of component fr om tape center 19.00 21.00 h0 lead wire clinch height 15.50 16.50 l1 lead wire (tape portion) 2.50 - d0 feed hole diameter 3.80 4.20 t1 taped lead thickness 0.35 0.45 t2 carrier tape thickness 0.15 0.25 p1 position of hole 3.55 4.15 p component alignment -1.00 1.00
cystech electronics corp. spec. no. : c233k3 issued date : 2013.05.09 revised date : 2013.12.25 page no. : 6/7 BTA1013K3 cystek product specification recommended wave soldering condition soldering time product peak temperature pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3 c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds 183 c 60-150 seconds time maintained above: ? temperature (t l ) 217 c ? time (t l ) 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak 10-30 seconds 20-40 seconds temperature(tp) ramp down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of t he package, measured on the package body surface.
cystech electronics corp. spec. no. : c233k3 issued date : 2013.05.09 revised date : 2013.12.25 page no. : 7/7 BTA1013K3 cystek product specification to-92l dimension *: typical inches millimeters inches millimeters dim min. max. min. max. a1013 marking: s t yle: pin 1.emitter 2.colle ctor 3.ba se 3-l ead t o -9 2l plasti c pa ckage cys t ek pa ck a g e code: k3 product name date code: y ear+month y ear: 7 2007, 8 20 08 9 9, a 10, b 11 , c 12 month: 1 1, 2 2, ??? , dim m i n . m a x . m i n . m a x . a 0 . 1 4 6 0 . 1 6 1 3 . 7 0 0 4 . 1 0 0 e 0 . 3 0 7 0 . 3 2 3 7 . 8 0 0 8 . 2 0 0 a 1 0 . 0 5 0 0 . 0 6 2 1 . 2 8 0 1 . 5 8 0 e * 0 . 0 5 * 1 . 2 7 0 b 0 . 0 1 4 0 . 0 2 2 0 . 3 5 0 0 . 5 5 0 e 1 0 . 0 9 6 0 . 1 0 4 2 . 4 4 0 2 . 6 4 0 b 1 0 . 0 2 4 0 . 0 3 1 0 . 6 0 0 0 . 8 0 0 l 0 . 5 4 3 0 . 5 5 9 1 3 . 8 0 0 1 4 . 2 0 0 c 0 . 0 1 4 0 . 0 1 8 0 . 3 5 0 0 . 4 5 0 ? - 0 . 0 6 3 - 1 . 6 0 0 d 0 . 1 8 5 0 . 2 0 1 4 . 7 0 0 5 . 1 0 0 h 0 . 0 0 0 0 . 0 1 2 0 . 0 0 0 0 . 3 0 0 d 1 0 . 1 5 7 - 4 . 0 0 0 - note s: 1.controlling dimension: millimeter s. 2.maximum lead thickness include s lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is an y q uestion w i th p a ck ing specification or p a cking metho d , please c ont act y our local c y s t ek sales of fice. material: ? lead: pur e tin plated ? mold compou n d : epoxy resin fa mily , flammabilit y solid burning cla ss: ul94v -0 im portan t n o tice : ? all rights are re served. reprod u c tion in w hole or in part is prohibited w i thout the p r ior w r itten a pprov al of c y stek. ? c y stek reserv es the right to m a ke changes to its products w i tho u t notice. ? cy st e k semic ond uct o r pr odu cts are n o t warr ante d t o be s u it able f o r use i n l i fe-su p p o rt a p p licatio ns, or sys tems. ? c y stek assumes no liability fo r an y consequenc e of customer pr oduct design, infringement of pat e n ts, or application assistance .
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